Course Details

MODULE 1: VLSI Digital Integrated Circuits

            This module provides MOS circuits: MOS transistor operation in linear and saturated regions, MOS transistor threshold voltage, MOS switch and inverter. Latch-up in CMOS inverter, Sheet resistance and area capacitances of layers, Wiring capacitances, CMOS inverter, CMOS Gates, Delays, Logical Effort, Electrical Effort, Gate sizing, Buffering, Asymmetric gate, Skewed gates, Ratioed logic, Switching power dissipation, Stick Diagram. MOSFET scaling: Constant-voltage, Constant-field scaling. Dynamic CMOS design: Steady-state behaviour of dynamic gate circuits, Noise considerations in dynamic design, Charge sharing, Cascading dynamic gates, Domino logic, np-CMOS logic, Problems in single- phase clocking, Two-phase non-overlapping clocking scheme.

Lab Module- Implementation and Testing using MAGIC and SPICE: NMOS and PMOS characteristics, Inverter characteristics, Flip Flop, Latches, Logic Gates, Counter, Adder, Multiplier and Sequence Detector.

MODULE 2: VLSI System Design

            This module provides Sequential Circuit Design- Sequencing Static Circuits: Sequencing Methods, Max Delay Constraints, Min Delay Constraints, Time borrowing, Clock Skew; The Bistability Principle; Circuit Design of Latches and Flip Flop: Conventional CMOS Latches, Conventional CMOS Flip Flops, Pulsed Latches, Resettable Latches and Flip Flop. Design of finite state machines: State Enumeration, FSM with Inputs. Datapath Subsystems- Addition/Subtraction: Single bit addition, Carry propagate Addition, Carry Ripple Adder, Carry generate and Propagation, PG Carry Ripple Addition, Carry Skip adder, Carry Look Ahead Adder, Carry Select Adder, Multiple-Input Addition; One /Zero Detectors; Comparator; Multiplication: Unsigned Array Multiplication, Booth Encoding, Serial-parallel implementations, Braun Multiplier, Baugh-Wooley Multiplier, Systolic array multipliers. Array Subsystem: Categories of memory array, SRAM: SRAM Cells, Row Circuitry, Column Circuitry, DRAM: Sub Array Architectures, Column Circuitry. Shifters: Barrel shifters, Logarithmic shifters. Area-time trade-off, Power consumption issues. Designing semiconductor memory and array structures: Memory core, Memory peripheral circuitry.

MODULE 3: VLSI DSP

            This module provides Iteration Bound: Data Flow Graph Representations, Loop Bound and Iteration Bound, Algorithms for computing Iteration Bound, Iteration Bound of Multi-rate Data Flow Graphs. Pipelining and Parallel Processing: Pipelining of FIR Digital Filters, Parallel Processing, Parallel Processing for Low Power. Retiming: Solving Systems of Inequalities, Retiming Techniques. Unfolding: Unfolding Algorithm, Properties of Unfolding, Critical Path, Unfolding and retiming, Applications of Unfolding. Folding: Folding Transformation, Register Minimization Techniques, Register Minimization in folded Architecture. Systolic Architecture Design: Systolic Array Design Methodology, FIR Systolic Arrays, Selection of Scheduling Vector, Matrix-Matrix Multiplication and 2D Systolic Array Design. Fast Convolution: Cook Toom Algorithm, Winograd Algorithm, Iterated Convolution, Cyclic Convolution.

MODULE 4: Hardware Description Language

          This module provides Introduction to digital circuit design flow, Verilog Language introduction, Levels of abstraction, Module, Ports types and declarations, Registers and nets, Arrays, Identifiers, Parameters, Relational, Arithmetic, Logical, Bit-wise shift Operators, Writing expressions, Behavioural Modelling, Structural Coding, Continuous Assignments, Procedural Statements, Always, Initial Blocks, begin end, fork join, Blocking and Non-blocking statements, Operation Control Statements, If, case, Loops: while, for-loop, forever, repeat, Combination and sequential circuit designs, Memory modelling,, state machines, CMOS gate modelling, Writing Tasks, Writing Functions, Compiler directives, Conditional Compilation, System Tasks, Gate level primitives, User defined primitives, Delays, Specify block, Testbenches, modelling, timing checks, Assertion based verification, Code for synthesis, Advanced topics, Writing reusable code.

MODULE 5: High Level Synthesis

                This module provides Chip Design Flow and Hardware Modelling, Introduction to HLS, Language front-end representation, Compiler Transformation in High Level Synthesis, Memory Modelling & Compiler Transformation in High Level Synthesis, Compiler Transformations in High Level Synthesis, Hardware Transformations & ASAP / ALAP Scheduling, Scheduling in High Level Synthesis, Force Directed Scheduling & Register Allocation, High Level Synthesis and Timing Issues, Finite State Machine Synthesis, Efficient Solution to Retiming & Introduction to Logic Synthesis, Introduction to Logic Synthesis.

MODULE 6: FPGA based Digital Implementation

                This module provides Introduction, Overview of HDL, FSM Implementation, Case Study: Filter Implementation- Critical Path, Timing Closure. FSM Implementation, Communication Protocols, IP Incorporation (BRAM, DSP, clock control, etc.), Case Study: Image Processing, Design flow for the design using system generator and Matlab Simulink, Design flow for system-level design with embedded hard/soft processor core together with FPGA, Design flow for high-level synthesis, using C as input language and Vivado synthesis tool, Project: Processor Design and Implementation

FEES

Course Break-up:

Certification